Design Engineering Architect

Company: Cadence Design Systems
Location: San Jose
Posted on: October 18, 2024

Job Description:

Design Engineering Architect
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Locations: SAN JOSE
Time Type: Full time
Posted on: Posted 4 Days Ago
Job Requisition ID: R47135
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
The Cadence Silicon Solution Group (SSG) develops industry-leading IPs that enable our customers in a variety of markets - from the endpoint to the edge to the cloud and AI for SoC and chiplets. At Cadence, we're helping set the standard on IP products that get integrated in SoCs and chiplets powering the world's Data Centers, Automobiles, Cloud, wired/Wireless, and AI-enabled systems. Cadence SSG IP business is growing fast. We're expanding our San Jose team and looking for smart, energetic, collaborative, and creative people to join this exciting growth opportunity and help us lead the industry with Cadence IP products for silicon solutions. Do you want to make a difference and be challenged?
Design Engineering Architect in physical design, SSG.
Responsibilities:

• This technical and project leadership role is responsible for working with IP design teams and silicon solution architects to develop new physical aware IP architectures, collaborating with leading foundries such as TSMC, Samsung, and Intel to achieve best Performance/Power/Area (PPA) for Cadence IPs, and guiding Cadence worldwide physical design teams to follow the best design practices and methodologies.
  
• The position requires 15+ years of experience in design tools, foundry technologies, and proven leadership in collaborating and coordinating cross-functional teams and external companies to develop industry-leading IPs for advanced technology nodes at world-leading semiconductor foundries.
  
• Cross-functional project management experience with strong communication and interpersonal skills are required.
  
• Thorough understanding and experience with the full physical design flows including RTL Synthesis, floorplan, P&R, high-performance clock-tree synthesis, static Timing analysis and closure, DFT, Low power design techniques, Physical verification.
  
• Deep knowledge and experience with Cadence tools/flows (Genus, Innovus, Voltus, Tempus, Modus, Conformal-LP, Pegasus).
  
• Good knowledge with high-performance interface PHYs and controllers is highly desirable.
  
  We're doing work that matters. Help us solve what others can't.
  Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences.
  Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For. Our shared passion for solving the world's toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence.
  Cadence is committed to creating a diverse environment and is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.
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Keywords: Cadence Design Systems, Sacramento , Design Engineering Architect, Engineering , San Jose, California